1. Field of the Invention
The present invention relates to a video disk player for reproducing video data signals from a video disk such as a laser video disk and, more specifically, to a video disk player including a special-reproduction signal processor circuit for reproducing a video data signal containing caption data for multiplexing characters.
2. Discussion of the Related Art
With variegation of video information, caption data, which is used for displaying character text on a display screen, is often superimposed on a video data signal. Video disk players have been developed which include special-reproduction signal processor circuits that can process such a video data signal containing caption data.
An example of a portion of a special-reproduction signal processor circuit used in a conventional video disk player, which stores input video data signals and makes special reproductions, such as frame feed, using the stored video data signals, is shown in FIG. 1. As shown in FIG. 1, the portion of the special-reproduction processor circuit comprises an A/D converter 1, memory 2, Y/C separator 3, D/A converters 4a and 4b, mixers 5a and 5b, sync generator 6, memory controller 7, adder 8, and D/A converter 9.
A video data signal containing caption data, which has been read from a video disk (not shown) and demodulated, is converted into a digital signal by A/D converter 1 and stored into memory 2. Memory 2 is capable of storing at least one field of video data. The operation of reading video data from and writing video data in the memory 2 is performed under control of memory controller 7 which produces read and write signals R and W, respectively. The video data signal read from memory 2 is applied to Y/C separator 3 where it is separated into a luminance signal Y and a chrominance signal C. Luminance signal Y and chrominance signal C are converted into analog signals by D/A converters 4a and 4b, respectively.
In order to minimize the capacity required for the memory 2, the sync signals of the video data signal stored in and, thus, read from memory 2 are removed. To add the sync signals back to the video data signal, mixers 5a and 5b mix reference sync signals, i.e., reference vertical sync signal V and reference horizontal sync signal H, that are generated by sync generator 6 with luminance signal Y and chrominance signal C to produce luminance signal Y' and chrominance signal C'. Reference vertical and horizontal sync signals V and H generated by sync generator 6 are also, applied to memory controller 7 and used by memory controller 7, for example, to time the resetting operation of the readout address signal.
Luminance signal Y' and chrominance signal C', each of which includes reference vertical sync signal V and reference horizontal sync signal H, are applied to output terminals Y'-OUT and C'-OUT, respectively. These signals are also applied to adder 8 where they are added together to produce a composite video data signal A. It should be noted that the video data signal read from memory 2 is converted to an analog signal by D/A converter 9 to produce a composite video data signal B.
The details of Y/C separator 3 are shown in FIG. 2. As shown in FIG. 2, Y/C separator 3 is based on a three-line comb filter and comprises 1H delay circuits 32 and 33, 1/4 coefficient circuits 31 and 35, 1/2 coefficient circuit 34, adders 36 and 37, and subtractor 38. It should be understood that Y/C separator 3 operates in connection with 1H delayed signals. Accordingly, luminance signal Y and chrominance signal C produced by Y/C separator 3 are phase-shifted by 1H with respect to the video data signal read from memory 2.
Various types of data, such as address data, control code data for controlling the player, caption data for displaying a character text on the display screen, etc., are located on a part of the vertical flyback period of the video disk. Of those types of data, the address and control code data, which are processed within the player, are separated from the video data signal before it is separated into Y and C signals. The caption data is processed in another video device (not shown), e.g., a TV set, including a demodulator, called a caption decoder. The caption decoder, therefore, separates the caption data from the video data signal after the video data signal passes through the Y/C separator 3.
As noted above, in Y/C separator 3 of FIG. 2, luminance signal Y and chrominance signal C are phase-shifted by 1H from the input video data signal. Because of this, the caption decoder necessarily picks up, for separation, caption data at an incorrect location and fails to decode the caption data. There are several techniques, however, for solving this problem. One approach uses a delay circuit for delaying the generation of reference vertical sync signal V by 1H. Another approach involves controlling memory controller 7 to start the read operation by 1H earlier. These techniques, however, have certain drawbacks.
In the first technique, sync generator 6 uses a high frequency oscillator, usually N.times.3.58 Mhz. If this is 4 fsc, for example, 910 stages of clock delay circuits are required for gaining a delay of 1H, because fsc=(455/2).times.f.sub.R. Use of such a great number of clock delay circuits is impractical.
In the second technique, in composite video data signal B shown in FIG. 1, the location where the caption data is superimposed appears 1H earlier than the location where the caption data would have been superimposed had the read operation not been started 1H earlier. The result will be a failure to decode the caption data.